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\journal{Computers \& Electrical Engineering}

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\title{Distributed Topology Discovery in Self-Assembled Nano Network-On-Chip}

%% Group authors per affiliation:
\author{Vincenzo Catania}
\ead{vincenzo.catania@dieei.unict.it}
\author{Andrea Mineo}
\ead{andrea.mineo@dieei.unict.it}
\author{Salvatore Monteleone}
\ead{salvatore.monteleone@dieei.unict.it}
\author{Davide Patti\corref{corr1}}
\ead{davide.patti@dieei.unict.it}
\address{DIEEI, University of Catania, v.le Andrea Doria 6, 95125 Catania, Italy}

\cortext[corr1]{Corresponding author}

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%\author{Vincenzo~Catania, Andrea Mineo, Salvatore Monteleone~and~Davide~Patti% 
%\thanks{The authors are with the Dipartimento di Ingegneria
%Elettrica, Elettronica ed Informatica, Universit\`a di Catania, Italy
%(email: \{vincenzo.catania,amineo,salvatore.monteleone,davide.patti\}@dieei.unict.it).}}

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\begin{abstract}
In this paper, we present \disr{}, a distributed approach to topology
discovery and defect mapping in a self-assembled nano
network-on-chip. The main aim is to achieve the already-proven
properties of segment-based deadlock freedom requiring neither 
a topology graph as input, nor a centralized algorithm to
configure network paths.  After introducing the conceptual elements
and the execution model of \disr{}, we show how the open-source Nanoxim
platform has been used to evaluate the proposed approach in the
process of discovering irregular network topology while establishing
network segments. Comparison against a tree-based approach shows how
\disr{} still preserves some important properties (coverage, defect
tolerance, scalability) while avoiding resource hungry solutions such
as virtual channels and hardware redundancy. Finally, we propose a
gate-level hardware implementation of the required control logic and
storage for \disr{}, demonstrating a relatively acceptable impact
ranging from 10 to about 20\% of the budget of transistors available
for each node.
\end{abstract}

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\begin{keyword}
Nanotechnology \sep DNA \sep Self-assembly \sep Routing \sep Deadlock
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\section{Conclusions}
In this work, we presented \disr{}, an initial attempt of achieving a segment based
topology discovery in a distributed self-assembled nanoscale scenario. We
demonstrated how \disr{} can accomplish the aim of finding a segment
coverage of the network without requiring any centralized approach
that would request the graph topology as input. A draft hardware
implementation has been presented to evaluate the impact on the limited
node size typical of the assumed scenario. From a high-level
perspective, future works will focus on
investigating \disr{} resulting networks in order to support the
execution of massively parallel applications, while continuing to
develop a detailed low level hardware implementation on a
DNA grid using the appropriate nano device models.

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\section*{References}
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\vspace{10 mm}

Vincenzo Catania received the Laurea degree in Electrical Engineering
from the University of Catania, Italy, in 1982. Until 1984, he was
responsible for testing microprocessor system at STMicroelectronics,
Catania. He is a full professor of computer
science. His research interests include performance and reliability
assessment in parallel and distributed system, VLSI design, low power
design, and fuzzy logic.

Andrea Mineo received the BSc and MSc degrees in Electronic
Engineering from the University of Catania, Italy, in 2010 and 2013,
respectively, and is currently pursuing the PhD degree in Systems,
Energy, Computer and Telecommunications Engineering at the University
of Catania. His current research interests are VLSI systems,
Network-on-Chip architectures and emerging interconnect technologies
for on-chip networks.

Salvatore Monteleone is a post-doctoral research assistant at the
Department of Electrical, Electronic and Computer Engineering -
University of Catania, Italy. He obtained the BSc (2007) and MSc
(2010) in Computer Engineering at University of Catania where he also
completed the PhD course in Communications and Computer Engineering
(2014). His interests comprehend cooperative systems, user-centric
systems and Network-on-Chip architectures.

Davide Patti received the Laurea and PhD degrees in computer
engineering from the University of Catania, Italy, in 2003 and 2007,
respectively. His research focuses on Design Space exploration of VLIW
systems, Network-on-Chip architectures, DNA self-assembled networks
and Human-computer interfaces. He is currently a research assistant
at University of Catania.

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